The present disclosure relates to an electronic circuit, a method of controlling the electronic circuit, and an electronic apparatus, and particularly to an electronic circuit provided with a time digital converter, a method of controlling the electronic circuit, and an electronic apparatus.
In the past, a time digital converter may be used to detect the phase of a clock signal in an electronic circuit. The time digital converter generally includes a plurality of stages of delay elements and a plurality of flip-flops. A plurality of delay signals, which are delayed clock signals, are generated by the plurality of delay elements. Data including values of the plurality of delay signals is stored in the flip-flop as a time-to-digital converter (TDC) code. If the respective delay times of the plurality of delay elements are the same as a predetermined design value, the phase of the clock signal can be accurately detected based on the TDC code. However, the delay time of the delay element in the time digital converter varies depending on conditions such as a process, a power source voltage, and a temperature. The delay time deviates from the design value due to the variation of the delay time, and thus, an error may occur in the phase represented by the TDC code.
In order to correct the error, a time digital converter including a plurality of stages of delay elements, each of which includes a transistor inserted between the respective power source terminals thereof as a current source, a flip-flop, and a calibration control circuit has been proposed (see, for example, Japanese Patent Application Laid-open No. 2012-114716). In the time digital converter, the calibration control circuit reads the TDC data from the flip-flop, and obtains an error in the TDC data. Then, the calibration control circuit corrects the amount of current flowing from the current source to the delay element to a value in which the error is reduced. With the correction of the current amount, the delay time of the delay element has a value close to the predetermined design value.